#ifndef __LTDC_H__
#define __LTDC_H__

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/poll.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/kthread.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <video/display_timing.h>
#include <video/of_display_timing.h>

typedef struct {
	volatile uint32_t IDR;				/*!< LTDC identification register                                  Address offset: 0x00 */
	volatile uint32_t LCR;				/*!< LDTC layer count register                                     Address offset: 0x04 */
	volatile uint32_t SSCR;				/*!< LTDC Synchronization Size Configuration Register,             Address offset: 0x08 */
	volatile uint32_t BPCR;				/*!< LTDC Back Porch Configuration Register,                       Address offset: 0x0C */
	volatile uint32_t AWCR;				/*!< LTDC Active Width Configuration Register,                     Address offset: 0x10 */
	volatile uint32_t TWCR;				/*!< LTDC Total Width Configuration Register,                      Address offset: 0x14 */
	volatile uint32_t GCR;				/*!< LTDC Global Control Register,                                 Address offset: 0x18 */
	volatile uint32_t GC1R;				/*!< LTDC global configuration 1 register,                         Address offset: 0x1C */
	volatile uint32_t GC2R;				/*!< LTDC global configuration 2 register,                         Address offset: 0x20 */
	volatile uint32_t SRCR;				/*!< LTDC Shadow Reload Configuration Register,                    Address offset: 0x24 */
	uint32_t RESERVED0[1];				/*!< Reserved, 0x28                                                                     */
	volatile uint32_t BCCR;				/*!< LTDC Background Color Configuration Register,                 Address offset: 0x2C */
	uint32_t RESERVED1[1];				/*!< Reserved, 0x30                                                                     */
	volatile uint32_t IER;				/*!< LTDC Interrupt Enable Register,                               Address offset: 0x34 */
	volatile uint32_t ISR;				/*!< LTDC Interrupt Status Register,                               Address offset: 0x38 */
	volatile uint32_t ICR;				/*!< LTDC Interrupt Clear Register,                                Address offset: 0x3C */
	volatile uint32_t LIPCR;			/*!< LTDC Line Interrupt Position Configuration Register,          Address offset: 0x40 */
	volatile uint32_t CPSR;				/*!< LTDC Current Position Status Register,                        Address offset: 0x44 */
	volatile uint32_t CDSR;				/*!< LTDC Current Display Status Register,                         Address offset: 0x48 */
	uint32_t RESERVED2[14];				/*!< Reserved, 0x4C                                                                     */
	volatile uint32_t L1CR;				/*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
	volatile uint32_t L1WHPCR;			/*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
	volatile uint32_t L1WVPCR;			/*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
	volatile uint32_t L1CKCR;			/*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
	volatile uint32_t L1PFCR;			/*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
	volatile uint32_t L1CACR;			/*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
	volatile uint32_t L1DCCR;			/*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
	volatile uint32_t L1BFCR;			/*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
	uint32_t L1RESERVED3[2];			/*!< Reserved */
	volatile uint32_t L1CFBAR;			/*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
	volatile uint32_t L1CFBLR;			/*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
	volatile uint32_t L1CFBLNR;			/*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
	uint32_t L1RESERVED4[3];			/*!< Reserved */
	volatile uint32_t L1CLUTWR;			/*!< LTDC Layerx CLUT Write Register                               Address offset: 0xC4 */
}ltdc_register_t;

#define LTDC_REGISTER_OFFSET			0x0000
#define LTDC_NUMBER						1

struct ltdc_handle{
	int use_flag;
	int backlight;
	struct fb_info *fb_info;
	unsigned int pseudo_palette[16];
	uint8_t *dma_buffer;
	uint8_t *fb_buffer;
	dma_addr_t fb_phy;
	uint32_t fb_size;
	ltdc_register_t *ltdc;
	struct clk *pixel_clk;
	struct display_timing *timing;
	int bus_width;
	int bits_per_pixel;
};

#endif
